{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T18:08:00Z","timestamp":1761588480882,"version":"build-2065373602"},"reference-count":20,"publisher":"IBM","issue":"4\/5","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IBM J. Res. &amp; Dev."],"published-print":{"date-parts":[[2018,7,1]]},"DOI":"10.1147\/jrd.2018.2847178","type":"journal-article","created":{"date-parts":[[2018,6,22]],"date-time":"2018-06-22T14:54:15Z","timestamp":1529679255000},"page":"12:1-12:10","source":"Crossref","is-referenced-by-count":16,"title":["IBM POWER9 package technology and design"],"prefix":"10.1147","volume":"62","author":[{"given":"S.","family":"Chun","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"W. D.","family":"Becker","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Casey","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Ostrander","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Dreps","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J. A.","family":"Hejase","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R. M.","family":"Nett","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B.","family":"Beaman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J. R.","family":"Eagle","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"3082","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1147\/rd.511.0053"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.40"},{"key":"ref12","first-page":"1900","article-title":"Development of a 50 mm dual flip chip plastic land grid array package for server applications","author":"ouimet","year":"0","journal-title":"Proc Electron Compon Technol Conf"},{"key":"ref13","article-title":"Low DF build-up material for high frequency signal. Transmission\n of substrates","author":"narahashi","year":"0","journal-title":"Proc 63rd Electron Compon Technol Conf"},{"key":"ref14","first-page":"523","article-title":"Advanced laminate carrier module warpage considerations for 32 nm Pb-free, FC PBGA package design and\n assembly","author":"blackshear","year":"0","journal-title":"Proc IEEE 61st Electron Compon Technol Conf"},{"key":"ref15","first-page":"1253","article-title":"Failure mechanism investigation of stacked via cracking in organic chip carrier","author":"li","year":"0","journal-title":"Proc Electron Compon Technol Conf"},{"key":"ref16","first-page":"491","article-title":"Correlation of dielectric film flex fatigue resistance and package resin cracking failure","author":"li","year":"0","journal-title":"Proc 67th Electron Compo Technol Conf"},{"key":"ref17","first-page":"236","article-title":"Engineered thermal interface material","author":"larson","year":"0","journal-title":"Proc IEEE 64th Electron Compon Technol Conf"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2010.5594694"},{"key":"ref19","first-page":"477","article-title":"Design considerations for 50G+ backplane links","author":"toifl","year":"0","journal-title":"Proc ESSCIRC Conf 42nd Eur Solid-State Circuits Conf"},{"key":"ref4","first-page":"187","article-title":"Design\n optimization for isolation in high wiring density packages with high speed SerDes links","author":"na","year":"0","journal-title":"Proc 56th Electron Compon Technol Conf"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2358553"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1147\/rd.494.0641"},{"key":"ref5","first-page":"1701","article-title":"Package and printed circuit board design of a 19.2 Gb\/s data link for high-performance computing","author":"chun","year":"0","journal-title":"Proc 67th Electron Compo Technol Conf"},{"year":"2017","key":"ref8","article-title":"OpenCAPI"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2015.2445031"},{"key":"ref2","doi-asserted-by":"crossref","DOI":"10.1147\/JRD.2018.2859564","article-title":"IBM POWER9 processor and system features for computing in the cognitive era","volume":"62","author":"arimilli","year":"2018","journal-title":"IBM J Res & Dev"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.466.0779"},{"key":"ref9","first-page":"1","article-title":"The 3rd generation of IBM's elastic interface on POWER6","author":"dreps","year":"0","journal-title":"IEEE Hot Chips 19 Symp"},{"year":"2015","key":"ref20","article-title":"DDR4 SDRAM registered DIMM design specification"}],"container-title":["IBM Journal of Research and Development"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5288520\/8458346\/08392682.pdf?arnumber=8392682","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T18:03:31Z","timestamp":1761588211000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8392682\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7,1]]},"references-count":20,"journal-issue":{"issue":"4\/5"},"URL":"https:\/\/doi.org\/10.1147\/jrd.2018.2847178","relation":{},"ISSN":["0018-8646","0018-8646"],"issn-type":[{"type":"print","value":"0018-8646"},{"type":"electronic","value":"0018-8646"}],"subject":[],"published":{"date-parts":[[2018,7,1]]}}}