{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,21]],"date-time":"2026-07-21T14:23:40Z","timestamp":1784643820921,"version":"3.55.0"},"reference-count":173,"publisher":"IBM","issue":"6","funder":[{"name":"Intel Science and Technology Center for Cloud Computing"},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100008047","name":"Carnegie Mellon University","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100008047","id-type":"DOI","asserted-by":"publisher"}]},{"name":"NSF","award":["1212962"],"award-info":[{"award-number":["1212962"]}]},{"name":"NSF","award":["1320531"],"award-info":[{"award-number":["1320531"]}]},{"name":"NSF","award":["1409723"],"award-info":[{"award-number":["1409723"]}]},{"DOI":"10.13039\/100000002","name":"National Institutes of Health","doi-asserted-by":"publisher","award":["HG006004"],"award-info":[{"award-number":["HG006004"]}],"id":[{"id":"10.13039\/100000002","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IBM J. Res. & Dev."],"published-print":{"date-parts":[[2019,11,1]]},"DOI":"10.1147\/jrd.2019.2934048","type":"journal-article","created":{"date-parts":[[2019,8,8]],"date-time":"2019-08-08T16:02:36Z","timestamp":1565280156000},"page":"3:1-3:19","source":"Crossref","is-referenced-by-count":142,"title":["Processing-in-memory: A workload-driven perspective"],"prefix":"10.1147","volume":"63","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9138-0613","authenticated-orcid":false,"given":"S.","family":"Ghose","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9748-845X","authenticated-orcid":false,"given":"A.","family":"Boroumand","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"J. S.","family":"Kim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"J.","family":"G\u00f3mez-Luna","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0075-2312","authenticated-orcid":false,"given":"O.","family":"Mutlu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"3082","reference":[{"key":"ref170","article-title":"Delay-optimal technology mapping for in-memory computing using ReRAM devices","author":"bhattacharjee","year":"2016","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Des"},{"key":"ref172","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2019.01.009"},{"key":"ref171","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2750064"},{"key":"ref173","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3323476"},{"key":"ref168","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00070"},{"key":"ref169","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203782"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2832911"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694774"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.21236\/ADA419598"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1994.108"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1999.808425"},{"key":"ref37","article-title":"JEDEC Solid State Technology Association, JESD235B: High Bandwidth Memory (HBM) DRAM Standard","year":"2018"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1970.5008902"},{"key":"ref35","first-page":"41","article-title":"The NON-VON database machine: A brief overview","volume":"4","author":"shaw","year":"1981","journal-title":"IEEE Database Eng Bull"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/40.592312"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1992.591879"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/54.748803"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/2.375174"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"107","DOI":"10.1016\/bs.adcom.2017.04.004","article-title":"Simple operations in memory to reduce data movement","volume":"106","author":"seshadri","year":"2017","journal-title":"Adv Comput"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322266"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750385"},{"key":"ref24","article-title":"LazyPIM: Efficient support for cache coherence in processing-in-memory architectures","author":"boroumand","year":"2017"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2016.2577557"},{"key":"ref101","article-title":"Co-architecting controllers and DRAM to enhance DRAM process scaling","author":"kang","year":"2014"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514197"},{"key":"ref100","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00040"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317867"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/1785414.1785441"},{"key":"ref154","doi-asserted-by":"publisher","DOI":"10.1145\/800015.808204"},{"key":"ref153","doi-asserted-by":"publisher","DOI":"10.1093\/bioinformatics\/btp324"},{"key":"ref156","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.13"},{"key":"ref155","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250697"},{"key":"ref150","doi-asserted-by":"publisher","DOI":"10.1093\/bioinformatics\/btx342"},{"key":"ref152","doi-asserted-by":"publisher","DOI":"10.1038\/ng.437"},{"key":"ref151","doi-asserted-by":"publisher","DOI":"10.1093\/bioinformatics\/btz234"},{"key":"ref146","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2821565"},{"key":"ref147","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00053"},{"key":"ref148","doi-asserted-by":"crossref","DOI":"10.1186\/1471-2164-14-S1-S13","article-title":"Accelerating read mapping with FastHASH","volume":"14","author":"xin","year":"2013","journal-title":"BMC Genomics"},{"key":"ref149","doi-asserted-by":"publisher","DOI":"10.1093\/bioinformatics\/btu856"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"ref58","first-page":"54","article-title":"STT-RAM scaling and retention failure","volume":"17","author":"naeimi","year":"2013","journal-title":"Intel Technol J"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"ref55","article-title":"Efficient data mapping and buffering techniques for multi-level cell phase-change memories","volume":"11","author":"yoon","year":"2014","journal-title":"ACM Trans Archit Code Optim"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2070050"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.24"},{"key":"ref40","article-title":"HMC Specification 2.0","year":"2014"},{"key":"ref167","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183532"},{"key":"ref166","article-title":"Ramulator for processing-in-memory – GitHub repository","year":"0"},{"key":"ref165","doi-asserted-by":"publisher","DOI":"10.14778\/2735508.2735511"},{"key":"ref164","doi-asserted-by":"publisher","DOI":"10.1007\/s004460050028"},{"key":"ref163","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598134"},{"key":"ref162","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1993.698569"},{"key":"ref161","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310767"},{"key":"ref160","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.41"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835958"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750392"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1186\/s12864-018-4460-0"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750386"},{"key":"ref159","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176241"},{"key":"ref8","first-page":"629","article-title":"Gaia: Geo-distributed machine learning approaching LAN speeds","author":"hsieh","year":"2017","journal-title":"Proc 10th USENIX Conf Netw Syst Des Implementation"},{"key":"ref49","article-title":"In-DRAM bulk bitwise execution engine","author":"seshadri","year":"2019"},{"key":"ref7","first-page":"269","article-title":"Focus: Querying large video datasets with low latency and low cost","author":"hsieh","year":"2018","journal-title":"Proc 10th USENIX Conf Oper Syst Des Implementation"},{"key":"ref157","doi-asserted-by":"publisher","DOI":"10.1109\/PERSER.2005.1506430"},{"key":"ref158","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250696"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2017.3641638"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317764"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196009"},{"key":"ref48","article-title":"Buddy-RAM: Improving the performance and efficiency of bulk bitwise operations using DRAM","author":"seshadri","year":"2016"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2434872"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2014.06.006"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"ref44","doi-asserted-by":"crossref","DOI":"10.1145\/3195970.3196092","article-title":"PIMA-Logic: A novel processing-in-memory architecture for highly flexible and energy-efficient logic computation","author":"angizi","year":"2018","journal-title":"Proc 55th Annu Des Autom Conf"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"ref127","doi-asserted-by":"publisher","DOI":"10.1145\/2442516.2442530"},{"key":"ref126","article-title":"TensorFlow Lite: For mobile & IoT","year":"0"},{"key":"ref125","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155664"},{"key":"ref124","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.46"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783764"},{"key":"ref129","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151013"},{"key":"ref71","article-title":"3D-stacked memory-side acceleration: Accelerator and system design","author":"guo","year":"2014","journal-title":"Proc Workshop Near-Data Process"},{"key":"ref128","doi-asserted-by":"publisher","DOI":"10.1016\/S0169-7552(98)00110-X"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001154"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2014.6855225"},{"key":"ref130","doi-asserted-by":"publisher","DOI":"10.1145\/2581122.2544162"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001178"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1145\/2818950.2818952"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001159"},{"key":"ref133","article-title":"MemSQL","year":"0"},{"key":"ref134","article-title":"SAP HANA","year":"0"},{"key":"ref131","doi-asserted-by":"publisher","DOI":"10.1145\/1807167.1807184"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1145\/3126908.3126965"},{"key":"ref132","doi-asserted-by":"publisher","DOI":"10.1145\/2600212.2600222"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.42"},{"key":"ref136","article-title":"Google Translate app","year":"0"},{"key":"ref135","first-page":"21","article-title":"The VoltDB main memory DBMS","volume":"36","author":"stonebraker","year":"2013","journal-title":"IEEE Data Eng Bull"},{"key":"ref138","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2015","journal-title":"Proc 3rd IAPR Asian Conf Pattern Recog"},{"key":"ref137","first-page":"630","article-title":"Identity mappings in deep residual networks","author":"he","year":"2016","journal-title":"Proc Eur Conf Comput Vis"},{"key":"ref60","doi-asserted-by":"crossref","first-page":"80","DOI":"10.1038\/nature06932","article-title":"The missing memristor found","volume":"453","author":"strukov","year":"2008","journal-title":"Nature"},{"key":"ref139","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.577"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2016.7753257"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.21"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783753"},{"key":"ref140","first-page":"4278","article-title":"Inception-v4, Inception-ResNet and the impact of residual connections on learning","author":"szegedy","year":"2017","journal-title":"Proc 31st AAAI Conf Artif Intell"},{"key":"ref65","first-page":"2069","article-title":"JAFAR: Near-Data processing for databases","author":"babarinsa","year":"2015","journal-title":"Proc ACM SIGMOD Int Conf Manage Data"},{"key":"ref141","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2016.7581275"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"ref142","article-title":"Gemmlowp: A small self-contained low-precision GEMM library","year":"0"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056040"},{"key":"ref143","article-title":"ARM Cortex-R8","year":"0"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.22"},{"key":"ref144","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00027"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446059"},{"key":"ref145","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00074"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2408776.2408794"},{"key":"ref109","first-page":"615","article-title":"Tiered-latency DRAM: A low latency and low cost DRAM architecture","author":"lee","year":"2013","journal-title":"Proc IEEE 19th Int Symp High Perform Comput Archit"},{"key":"ref95","first-page":"782","article-title":"ReVAMP: ReRAM based VLIW architecture for in-memory computing","author":"bhattacharjee","year":"2017","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref108","doi-asserted-by":"publisher","DOI":"10.1145\/2896377.2901453"},{"key":"ref94","first-page":"427","article-title":"The programmable logic-in-memory (PLiM) computer","author":"gaillardon","year":"2016","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref107","doi-asserted-by":"crossref","first-page":"187","DOI":"10.1147\/rd.462.0187","article-title":"Challenges and future directions for the scaling of dynamic random-access memory (DRAM)","volume":"46","author":"mandelman","year":"2002","journal-title":"IBM J Res Develop"},{"key":"ref93","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2282132"},{"key":"ref106","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2915318"},{"key":"ref92","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081389"},{"key":"ref105","first-page":"361","article-title":"Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors","author":"kim","year":"2014","journal-title":"Proc 41st Annu Int Symp Comput Archit"},{"key":"ref91","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2013.6670336"},{"key":"ref104","first-page":"19","article-title":"Research problems and opportunities in memory systems","volume":"1","author":"mutlu","year":"2014","journal-title":"International Journal on Supercomputing Frontiers and Innovations"},{"key":"ref90","doi-asserted-by":"publisher","DOI":"10.1145\/2600212.2600213"},{"key":"ref103","first-page":"1116","article-title":"The RowHammer problem and other issues we may face as memory becomes denser","author":"mutlu","year":"2017","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref102","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582088"},{"key":"ref111","doi-asserted-by":"publisher","DOI":"10.1145\/3143314.3078533"},{"key":"ref112","doi-asserted-by":"publisher","DOI":"10.1145\/3309697.3331482"},{"key":"ref110","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056057"},{"key":"ref98","first-page":"722","article-title":"Memristor for computing: Myth or reality?","author":"hamdioui","year":"2017","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref99","first-page":"1646","article-title":"Memristive devices for computation-in-memory","author":"yu","year":"2018","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref96","first-page":"1718","article-title":"Memristor based computation-in-memory architecture for data-intensive applications","author":"hamdioui","year":"2015","journal-title":"Proc Des Autom Test Eur Conf Exhib"},{"key":"ref97","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357122"},{"key":"ref10","article-title":"JEDEC Solid State Technology Association, JESD79-3F: DDR3 SDRAM Standard","year":"2012"},{"key":"ref11","article-title":"JEDEC Solid State Technology Association, JESD79-4B: DDR4 SDRAM Standard","year":"2017"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.51"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-90385-9_5"},{"key":"ref14","article-title":"Enabling the adoption of processing-in-memory: Challenges, mechanisms, future research directions","author":"ghose","year":"2018"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.89"},{"key":"ref118","article-title":"Accelerating bulk bit-wise X(N)OR operation in processing-in-DRAM platform","author":"angizi","year":"2019"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173177"},{"key":"ref82","article-title":"A processing in memory taxonomy and a case for studying fixed-function PIM","author":"loh","year":"2013","journal-title":"Proc 3rd Workshop Near-Data Process"},{"key":"ref117","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750397"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446095"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1145\/3087556.3087582"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.54"},{"key":"ref119","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037702"},{"key":"ref19","first-page":"185","article-title":"RowClone: Fast and Energy-Efficient in-DRAM Bulk Data Copy and Initialization","author":"vivek seshadri","year":"2013","journal-title":"2013 46th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1145\/2686875"},{"key":"ref114","doi-asserted-by":"publisher","DOI":"10.1145\/3084447"},{"key":"ref113","doi-asserted-by":"publisher","DOI":"10.1145\/3224419"},{"key":"ref116","year":"2014"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123977"},{"key":"ref115","year":"2011"},{"key":"ref120","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080233"},{"key":"ref89","article-title":"Data access optimization in a processing-in-memory system","author":"sura","year":"2015","journal-title":"Proc 12th ACM Int Conf Comput Frontiers"},{"key":"ref121","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"ref122","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.33"},{"key":"ref123","article-title":"ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers","author":"kim","year":"2010","journal-title":"Proc Int Symp High-Perform Comput Archit"},{"key":"ref85","first-page":"31","article-title":"Scheduling techniques for GPU architectures with processing-in-memory capabilities","author":"pattnaik","year":"2016","journal-title":"Proc Int Conf Parallel Archit Compil"},{"key":"ref86","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844483"},{"key":"ref87","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830820"},{"key":"ref88","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"}],"container-title":["IBM Journal of Research and Development"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5288520\/8894910\/08792187.pdf?arnumber=8792187","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,20]],"date-time":"2025-10-20T17:55:28Z","timestamp":1760982928000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8792187\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11,1]]},"references-count":173,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1147\/jrd.2019.2934048","relation":{},"ISSN":["0018-8646","0018-8646"],"issn-type":[{"value":"0018-8646","type":"print"},{"value":"0018-8646","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,11,1]]}}}