{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T11:05:26Z","timestamp":1740135926435,"version":"3.37.3"},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":2191,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1994,1]]},"abstract":"<jats:p>While the performance, density, and complexity of application\u2010specific systems increase at a rapid pace, equivalent\nadvances are not being made in making them more easily testable, diagnosable, and maintainable. Even though\ntestability bus standards, like JTAG Boundary Scan, have been developed to help eliminate these costs, there\nexists a need for efficient hardware and software tools to support them. Hence, a testability design and hardware\nsupport environment for application\u2010specific systems is described which provides a designer with a set of hardware\nmodules and circuitry, that support these standards and software tools for automatic incorporation of testability\nhardware, as well as automatic test vector and test program generation.<\/jats:p>","DOI":"10.1155\/1994\/39791","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:36:02Z","timestamp":1190118962000},"page":"345-357","source":"Crossref","is-referenced-by-count":0,"title":["Integrated Test Solutions for a System DesignEnvironment"],"prefix":"10.1155","volume":"1","author":[{"given":"Kevin T.","family":"Kornegay","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Robert W.","family":"Brodersen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1994,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1994\/039791.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1994\/39791","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:33:20Z","timestamp":1723203200000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1994\/39791"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1994,1]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1994,1]]}},"alternative-id":["10.1155\/1994\/39791"],"URL":"https:\/\/doi.org\/10.1155\/1994\/39791","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1994,1]]}}}