{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T12:10:03Z","timestamp":1723205403085},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":2191,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1994,1]]},"abstract":"<jats:p>The logic behavior and performance of ECL gates under a set of defect models are examined. These are compared\nwith equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaining\na sufficiently high fault coverage, e.g., 79% for ECL versus 54% for BiCMOS and 69% for CMOS equivalent\ngates. Performance degradation faults such as delay, current and Voltage Transfer Characteristics (VTC) or Noise\nMargin (NM) faults are analyzed as applied to these gates. It is shown that logical fault testing with delay fault\ntesting yields the highest fault coverage for BiCMOS and CMOS gates (around 95%). However, for equivalent\nECL gates to attain a fault coverage of around 98%, both logical and NM fault testing have to be used.<\/jats:p>","DOI":"10.1155\/1994\/70696","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:36:02Z","timestamp":1190118962000},"page":"261-276","source":"Crossref","is-referenced-by-count":3,"title":["Fault Characterization and Testability Analysis ofEmitter Coupled Logic and Comparison with CMOS&amp; BiCMOS Circuits"],"prefix":"10.1155","volume":"1","author":[{"given":"M. O.","family":"Esonu","sequence":"first","affiliation":[]},{"given":"D.","family":"Al-Khalili","sequence":"additional","affiliation":[]},{"given":"C.","family":"Rozon","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1994,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1994\/070696.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1994\/70696","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:33:17Z","timestamp":1723203197000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1994\/70696"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1994,1]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1994,1]]}},"alternative-id":["10.1155\/1994\/70696"],"URL":"https:\/\/doi.org\/10.1155\/1994\/70696","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1994,1]]}}}