{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T10:27:15Z","timestamp":1742380035424},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":2191,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1994,1]]},"abstract":"<jats:p>On\u2010the\u2010fly calculations of area and performance are a typical part of the computer\u2010aided iterative design process\nin VLSI, which aims at a satisfactory tradeoff of various conflicting objectives, among which are test\u2010generation\ntime and test\u2010set size. However, determining test sets on\u2010the\u2010fly as one circuit is transformed into another is\nextremely difficult. Our goal is to add a test dimension to the design optimization process that complements\nmethods concerned with area and performance optimization. We define a set of logic transformations that result\nin easily computed changes to test sets. Test\u2010set preserving (TSP) transformations preserve a combinational circuit\u2019s\ntest sets, while test\u2010set altering (TSA) transformations introduce a minimum number of tests needed to maintain\ncompleteness. We illustrate our approach with a family of adders that share area\u2010efficient tree structures and\ndiffer in the amount of carry\u2010lookahead used to accelerate carry computation. Members include the ripple\u2010carry\nadder, which has no lookahead, and the standard carry\u2010lookahead adder, which exploits lookahead across all\ninputs. It is straightforward to derive area and performance measures for this class of adders. Given an <jats:italic>n<\/jats:italic>\u2010bit\nadder with lookahead degree <jats:italic>k<\/jats:italic>, we determine a sequence of circuit transformations that produce the adder of\ndegree <jats:italic>k<\/jats:italic><jats:sup>2<\/jats:sup> and test sets of minimum size. Optimal test sets of size <jats:italic>k<\/jats:italic>(log<jats:sub>k<\/jats:sub><jats:italic>n<\/jats:italic> + 1) + 2 result for arbitrary <jats:italic>n<\/jats:italic> and <jats:italic>k<\/jats:italic>,\nwhich improve significantly upon previously reported tests.<\/jats:p>","DOI":"10.1155\/1994\/74269","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:36:02Z","timestamp":1190118962000},"page":"285-298","source":"Crossref","is-referenced-by-count":3,"title":["Optimal Testing and Design of Adders"],"prefix":"10.1155","volume":"1","author":[{"given":"Michael J.","family":"Batek","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John P.","family":"Hayes","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1994,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1994\/074269.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/vlsi\/1994\/074269.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1994\/74269","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:33:12Z","timestamp":1723203192000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1994\/74269"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1994,1]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1994,1]]}},"alternative-id":["10.1155\/1994\/74269"],"URL":"https:\/\/doi.org\/10.1155\/1994\/74269","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1994,1]]}}}