{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T00:10:07Z","timestamp":1723075807842},"reference-count":0,"publisher":"Wiley","issue":"3","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":2489,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1994,1]]},"abstract":"<jats:p>The testability distribution of a VLSI circuit is modeled as a series of step functions over the interval [0, 1]. The\nmodel generalizes previous related work on testability. Unlike previous work, however, we include estimates of\ntestability by random vectors. Quadratic programming methods are used to estimate the parameters of the\ntestability distribution from fault coverage data (random and deterministic) on a sample of faults. The estimated\ntestability is then used to predict the random and deterministic fault coverage distributions <jats:italic>without<\/jats:italic>  the need to\nemploy test generation or fault simulations. The prediction of fault coverage distribution can answer important\nquestions about the \u201cgoodness\u201d of a design from a testing point of view. Experimental results are given on the\nlarge ISCAS\u201085 and ISCAS\u201089 circuits.<\/jats:p>","DOI":"10.1155\/1994\/75615","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:35Z","timestamp":1190120195000},"page":"223-231","source":"Crossref","is-referenced-by-count":0,"title":["A Quadratic Programming Approach to Estimatingthe Testability and Random or DeterministicCoverage of a VLSl Circuit"],"prefix":"10.1155","volume":"2","author":[{"given":"H.","family":"Farhat","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"From","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1993,3,9]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1994\/075615.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/vlsi\/1994\/075615.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1994\/75615","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T23:53:13Z","timestamp":1723074793000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1994\/75615"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,3,9]]},"references-count":0,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1994,1]]}},"alternative-id":["10.1155\/1994\/75615"],"URL":"https:\/\/doi.org\/10.1155\/1994\/75615","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1993,3,9]]}}}