{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,15]],"date-time":"2024-09-15T22:47:17Z","timestamp":1726440437284},"reference-count":0,"publisher":"Wiley","issue":"3","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":2481,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1994,1]]},"abstract":"<jats:p>In this paper, we present a Simulated Evolution Gate Matrix layout Algorithm (SEGMA) for synthesizing CMOS\nrandom logic modules. The gate\u2010matrix layout problem is solved as a one\u2010dimensional transistor gates placement\nproblem. Given a placement of all the transistor gates, simulated evolution offers a systematic method to improve\nthe quality of the layout that is measured by the number of tracks needed for the given netlist. This is accomplished\nby identifying a subset of gates whose relative placements are deemed \u201cpoor quality\u201d according to a heuristic\ncriterion. By rearranging the placement of these identified subsets of gates, it is hoped that a gate placement with\nbetter quality, meaning fewer tracks, may emerge. Since this method enables the current \u201cgeneration\u201d of gate\nplacement to evolve into a more advanced one in a way similar to the biological evolution process, this method\nis called <jats:italic>simulated evolution<\/jats:italic>. To apply simulated evolution to solve the gate\u2010matrix layout problem, we propose\na novel heuristic criterion, called randomized quality factor, which facilitates the judicious selection of the subset\nof poor quality gates. Several carefully devised and tested strategies are also implemented. Extensive simulation\nresults indicate that SEGMA is producing very compact gate\u2010matrix layouts.<\/jats:p>","DOI":"10.1155\/1994\/80287","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:35Z","timestamp":1190120195000},"page":"241-257","source":"Crossref","is-referenced-by-count":1,"title":["SEGMA: A Simulated Evolution Gate\u2010Matrix LayoutAlgorithm"],"prefix":"10.1155","volume":"2","author":[{"given":"Chi-Yu","family":"Mao","sequence":"first","affiliation":[]},{"given":"Yu Hen","family":"Hu","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1993,3,17]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1994\/080287.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1994\/80287","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T23:53:11Z","timestamp":1723074791000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1994\/80287"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,3,17]]},"references-count":0,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1994,1]]}},"alternative-id":["10.1155\/1994\/80287"],"URL":"https:\/\/doi.org\/10.1155\/1994\/80287","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1993,3,17]]}}}