{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,26]],"date-time":"2025-10-26T14:11:59Z","timestamp":1761487919059},"reference-count":0,"publisher":"Wiley","issue":"3-4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1826,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1995,1]]},"abstract":"<jats:p>Modem microelectronic technology.gives opportunities to build digital circuits of huge complexity and provides a wide\ndiversity of logic building blocks. Although logic designers have been building circuits for many years, they have realized\nthat advances in microelectronic technology are outstripping their abilities to make use of the created opportunities. In this\npaper, we present the fundamentals of a logic design methodology which meets the requirements of today\u2032s complex circuits\nand modem building blocks. The methodology is based on the theory of general full\u2010decompositions which constitutes the\ntheory of digital circuit structures at the highest abstraction level. The paper explains the theory and shows how it can be\nused for digital circuit synthesis. The decomposition methodology that is presented ensures \u201ccorrectness by construction\u201d\nand enables very effective and efficient post\u2010factum validation. It makes possible extensive examination of the structural\nfeatures of the required information processing in relation to a given set of objectives and constraints.<\/jats:p>","DOI":"10.1155\/1995\/16259","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:46Z","timestamp":1190120206000},"page":"225-248","source":"Crossref","is-referenced-by-count":25,"title":["General Decomposition and Its Use in Digital Circuit Synthesis"],"prefix":"10.1155","volume":"3","author":[{"given":"Lech","family":"J\u00f3\u017awiak","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1995,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1995\/016259.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1995\/16259","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:39:49Z","timestamp":1723070389000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1995\/16259"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,1]]},"references-count":0,"journal-issue":{"issue":"3-4","published-print":{"date-parts":[[1995,1]]}},"alternative-id":["10.1155\/1995\/16259"],"URL":"https:\/\/doi.org\/10.1155\/1995\/16259","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1995,1]]}}}