{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T10:10:02Z","timestamp":1723198202786},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":2244,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1995,1]]},"abstract":"<jats:p>We present an integrated and optimal solution to the problems of operator scheduling, module and register\nallocation, and operator binding in datapath synthesis. The solution is based on an integer linear programming\n(ILP) model that minimizes a weighted sum of module area and total execution time under very general\nassumptions of module capabilities. In particular, a module may execute an arbitrary combination of operations,\npossibly using different numbers of control steps for different operations. Furthermore, operations may be\nimplemented by a variety of modules, possibly requiring different numbers of control steps depending on the\nmodules chosen. This generality in the complexity and mixture of modules is unqiue to our system and leads to an\noptimum selection of modules to meet specified design constraints. Significant extensions include the ability to\nincorporate pipelined functional units and operator chaining in an integrated manner. Straightforward extension\nto multi\u2010block synthesis is discussed briefly but the details are omitted due to space considerations.<\/jats:p>","DOI":"10.1155\/1995\/23249","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:46Z","timestamp":1190120206000},"page":"21-36","source":"Crossref","is-referenced-by-count":7,"title":["An ILP Solution for Optimum Scheduling, Moduleand Register Allocation, and OperationBinding in Datapath Synthesis"],"prefix":"10.1155","volume":"3","author":[{"given":"T. C.","family":"Wilson","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Mukherjee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M. K.","family":"Garg","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D. K.","family":"Banerji","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1993,11,9]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1995\/023249.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1995\/23249","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T09:44:17Z","timestamp":1723196657000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1995\/23249"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,11,9]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1995,1]]}},"alternative-id":["10.1155\/1995\/23249"],"URL":"https:\/\/doi.org\/10.1155\/1995\/23249","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1993,11,9]]}}}