{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T23:40:02Z","timestamp":1723074002256},"reference-count":0,"publisher":"Wiley","issue":"3-4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1826,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1995,1]]},"abstract":"<jats:p>This paper presents a methodology and a tool box for system\u2010level partitioning in the behavioral domain. The methodology\nis based on an extended finite state machine model. Partitioning is achieved interactively through the application of five\nsystem\u2010level transformation primitives: MOVE, MERGE, SPLIT, CUT and MAP. This scheme allows an interactive\nexploration of the solution space. The result of the partitioning is a set of interconnected and heterogeneous sub\u2010systems.\nThe partitioning tool box which has been developed is named PARTIE PARTIF includes an evaluation feedback loop that\nhelps the designer estimate the quality of the design.<\/jats:p>","DOI":"10.1155\/1995\/28167","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:46Z","timestamp":1190120206000},"page":"333-345","source":"Crossref","is-referenced-by-count":1,"title":["PARTIF: Interactive System\u2010level Partitioning"],"prefix":"10.1155","volume":"3","author":[{"given":"Tarek Ben","family":"Ismail","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kevin","family":"O\u2032Brien","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ahmed","family":"Jerraya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1995,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1995\/028167.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1995\/28167","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:39:44Z","timestamp":1723070384000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1995\/28167"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,1]]},"references-count":0,"journal-issue":{"issue":"3-4","published-print":{"date-parts":[[1995,1]]}},"alternative-id":["10.1155\/1995\/28167"],"URL":"https:\/\/doi.org\/10.1155\/1995\/28167","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1995,1]]}}}