{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T10:10:02Z","timestamp":1723198202853},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":2292,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1995,1]]},"abstract":"<jats:p>Recently a novel clock distribution scheme called Branch\u2010and\u2010Combine(BaC) has been proposed. The scheme\nguarantees constant skew bound irrespective of the size of the clocked network. It utilizes simple nodes to process\nclock signals such that clock paths are adaptively selected to guarantee constant skew bound. The paper uses a\nVLSI model to compare the properties of the new scheme to those of the well established H\u2010Tree approach. The\nH\u2010Tree is a binary tree of simple buffers which is laid out such that leaves are at equal distances from the root.\nOur study considers clocking 2\u2010D processor meshes of arbitrary sizes. We evaluate and compare the relevant\nparameters of both schemes in a VLSI layout context. We utilize parameters such as clock skew, link costs, node\ncosts and area efficiency as the basis for comparison. We show that for each BaC network, there is a certain\nthreshold size after which it outperforms the corresponding tree network in terms of skew. We also show that\nexcept for node costs, BaC networks outperform the H\u2010Tree, especially when the size of the clocked network is\nlarge. As an extension we show that BaC clocking does not suffer from potential pulse disappearance, no matter\nhow large the network is.<\/jats:p>","DOI":"10.1155\/1995\/35157","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:46Z","timestamp":1190120206000},"page":"81-92","source":"Crossref","is-referenced-by-count":2,"title":["A Comparative Study of SynchronousClocking Schemes for VLSI Based Systems"],"prefix":"10.1155","volume":"3","author":[{"given":"Ahmed","family":"El-Amawy","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Umasankar","family":"Maheshwar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1993,9,22]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1995\/035157.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1995\/35157","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T09:44:15Z","timestamp":1723196655000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1995\/35157"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,9,22]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1995,1]]}},"alternative-id":["10.1155\/1995\/35157"],"URL":"https:\/\/doi.org\/10.1155\/1995\/35157","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1993,9,22]]}}}