{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T23:40:02Z","timestamp":1723074002539},"reference-count":0,"publisher":"Wiley","issue":"3-4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1826,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1995,1]]},"abstract":"<jats:p>Here we present a new method for the decomposition of a Finite State Machine (FSM) into a network of interacting FSMs\nand a framework for the functional verification of the FSM network at different levels of abstraction. The problem of\ndecomposition is solved by output partitioning and state space decomposition using a multiway graph partitioning\ntechnique. The number of submachines is determined dynamically during the partitioning process. The verification\nalgorithm can be used to verify (a) the result of FSM decomposition on a behavioral level, (b) the encoded FSM network,\nand (c) the FSM network after logic optimization. Our verification technique is based on an efficient enumeration\u2010simulation\nmethod which involves traversal of the state transition graph of the prototype machine and simulation of the decomposed\nmachine network. Both the decomposition and verification\/simulation algorithms have been implemented as part of an\ninteractive FSM synthesis system and tested on a set of benchmark examples.<\/jats:p>","DOI":"10.1155\/1995\/62636","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:46Z","timestamp":1190120206000},"page":"249-265","source":"Crossref","is-referenced-by-count":1,"title":["FSM Decomposition and Functional Verification ofFSM Networks"],"prefix":"10.1155","volume":"3","author":[{"given":"Zafar","family":"Hasan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maciej J.","family":"Ciesielski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1995,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1995\/062636.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1995\/62636","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:39:34Z","timestamp":1723070374000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1995\/62636"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,1]]},"references-count":0,"journal-issue":{"issue":"3-4","published-print":{"date-parts":[[1995,1]]}},"alternative-id":["10.1155\/1995\/62636"],"URL":"https:\/\/doi.org\/10.1155\/1995\/62636","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1995,1]]}}}