{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,4]],"date-time":"2026-06-04T09:03:15Z","timestamp":1780563795333,"version":"3.54.1"},"reference-count":0,"publisher":"Wiley","issue":"3-4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1826,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1995,1]]},"abstract":"<jats:p>An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in this\npaper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representation\nof the function by a set of r\u2010partitions over the set of minterms. Two different decomposition strategies, namely serial and\nparallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completely\nor incompletely specified, single\u2010 or multiple\u2010output functions and is suitable for different types of FPGAs including\nXILINX, ACTEL and ALGOTRONIX devices. The results of the benchmark experiments presented in the paper show that,\nin several cases, our method produces circuits of significantly reduced complexity compared to the solutions reported in the literature.<\/jats:p>","DOI":"10.1155\/1995\/67208","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:46Z","timestamp":1190120206000},"page":"289-300","source":"Crossref","is-referenced-by-count":36,"title":["A General Approach to Boolean FunctionDecomposition and its Application in FPGABasedSynthesis"],"prefix":"10.1155","volume":"3","author":[{"given":"Tadeusz","family":"\u0141uba","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Henry","family":"Selvaraj","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"311","published-online":{"date-parts":[[1995,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1995\/067208.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1995\/67208","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:39:48Z","timestamp":1723070388000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1995\/67208"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,1]]},"references-count":0,"journal-issue":{"issue":"3-4","published-print":{"date-parts":[[1995,1]]}},"alternative-id":["10.1155\/1995\/67208"],"URL":"https:\/\/doi.org\/10.1155\/1995\/67208","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"value":"1065-514X","type":"print"},{"value":"1563-5171","type":"electronic"}],"subject":[],"published":{"date-parts":[[1995,1]]}}}