{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T23:40:02Z","timestamp":1723074002491},"reference-count":0,"publisher":"Wiley","issue":"3-4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1826,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1995,1]]},"abstract":"<jats:p>This paper introduces a new design approach that combines stages of logic and physical design. The logic function is\nsynthesized and mapped to a two\u2010dimensional array of logic cells. This array generalizes PLAs, XPLAs and cellular Maitra\ncascades. Each cell can be programmed to a wire, an inverter, or a two\u2010input AND, OR or EXOR gate (with any subset of\ninputs negated). The gate can take any output of four neighbor cells and four neighbor buses as its inputs, and sends its result\nback to them. This two\u2010dimensional geometrical model is well suited for both fine\u2010grain FPGA realization and sea\u2010of\u2010gates\ncustom ASIC layout. The comprehensive design method starts from a Boolean function, specified as SOP or ESOP, and\nproduces a rectangularly shaped structure of (mostly) locally connected cells. Two stages: restricted factorization, and\ncolumn folding, are discussed in more details to illustrate our general methodology.<\/jats:p>","DOI":"10.1155\/1995\/70871","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:46Z","timestamp":1190120206000},"page":"315-332","source":"Crossref","is-referenced-by-count":4,"title":["A New Design Methodology for Two\u2010DimensionalLogic Arrays"],"prefix":"10.1155","volume":"3","author":[{"given":"Ning","family":"Song","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marek A.","family":"Perkowski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Malgorzata","family":"Chrzanowska-Jeske","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andisheh","family":"Sarabi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1995,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1995\/070871.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1995\/70871","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:39:35Z","timestamp":1723070375000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1995\/70871"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,1]]},"references-count":0,"journal-issue":{"issue":"3-4","published-print":{"date-parts":[[1995,1]]}},"alternative-id":["10.1155\/1995\/70871"],"URL":"https:\/\/doi.org\/10.1155\/1995\/70871","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1995,1]]}}}