{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T10:10:02Z","timestamp":1723198202085},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":2191,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1995,1]]},"abstract":"<jats:p>A formal approach for the transformation of computation intensive digital signal processing algorithms into\nsuitable array processor architectures is presented. It covers the complete design flow from algorithmic specifications\nin a high\u2010level programming language to architecture descriptions in a hardware description language. The\ntransformation itself is divided into manageable design steps and implemented in the CAD\u2010tool DECOMP which\nallows the exploration of different architectures in a short time. With the presented approach data independent\nalgorithms can be mapped onto array processor architectures. To allow this, a known mapping methodology for\narray processor design is extended to handle inhomogeneous dependence graphs with nonregular data dependences.\nThe implementation of the formal approach in the DECOMP is an important step towards design\nautomation for massively parallel systems.<\/jats:p>","DOI":"10.1155\/1995\/76861","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:46Z","timestamp":1190120206000},"page":"67-80","source":"Crossref","is-referenced-by-count":0,"title":["Stepwise Transformation of Algorithmsinto Array Processor Architecturesby the DECOMP"],"prefix":"10.1155","volume":"3","author":[{"given":"Uwe","family":"Vehlies","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1994,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1995\/076861.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1995\/76861","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T09:44:19Z","timestamp":1723196659000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1995\/76861"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1994,1]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1995,1]]}},"alternative-id":["10.1155\/1995\/76861"],"URL":"https:\/\/doi.org\/10.1155\/1995\/76861","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1994,1]]}}}