{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T12:10:03Z","timestamp":1723205403750},"reference-count":0,"publisher":"Wiley","issue":"3","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1461,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1996,1]]},"abstract":"<jats:p>A novel path delay fault simulator for combinational logic circuits which is capable of\ndetecting both robust and nonrobust paths is presented. Particular emphasis has been given\nfor the use of binary logic rather than the multiple\u2010valued logic as used in the existing\nsimulators which contributes to the reduction of the overall complexity of the algorithm. A\nrule based approach has been developed which identifies all robust and nonrobust paths\ntested by a two\u2010pattern test &lt;V1,V2&gt;, while backtracing from the POs to PIs in a depth\u2010first\nmanner. Rules are also given to find probable glitches and to determine how they propagate\nthrough the circuit, which enables the identification of nonrobust paths. Experimental results\non several ISCAS\u203285 benchmark circuits demonstrate the efficiency of the algorithm.<\/jats:p>","DOI":"10.1155\/1996\/25839","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:50Z","timestamp":1190120210000},"page":"167-179","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["A Novel Path Delay Fault Simulator Using Binary Logic"],"prefix":"10.1155","volume":"4","author":[{"given":"Ananta K.","family":"Majhi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James","family":"Jacob","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lalit M.","family":"Patnaik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1996,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1996\/025839.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1996\/25839","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:44:26Z","timestamp":1723203866000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1996\/25839"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1996,1]]},"references-count":0,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1996,1]]}},"alternative-id":["10.1155\/1996\/25839"],"URL":"https:\/\/doi.org\/10.1155\/1996\/25839","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1996,1]]},"assertion":[{"value":"1996-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}