{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:40:01Z","timestamp":1723203601549},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1797,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["MIP-9208293"],"award-info":[{"award-number":["MIP-9208293"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1996,1]]},"abstract":"<jats:p>Placement is an important constrained optimization problem in the design of very large scale\n(VLSI) integrated circuits [1\u20134]. Simulated annealing [5] and min\u2010cut placement [6] are two\nof the most successful approaches to the placement problem. Min\u2010cut methods yield less\ncongested and more routable placements at the expense of more wire\u2010length, while simulated\nannealing methods tend to optimize more the total wire\u2010length with little emphasis on the\nminimization of congestion. It is also well known that min\u2010cut algorithms are substantially\nfaster than simulated\u2010annealing\u2010based methods. In this paper, a fast min\u2010cut algorithm\n(ROW\u2010PLACE) for row\u2010based placement is presented and is empirically shown to achieve\nsimulated\u2010annealing\u2010quality wire\u2010length on a number of benchmark circuits. In comparison\nwith Timberwolf 6 [7], ROW\u2010PLACE is at least 12 times faster in its normal mode and is at\nleast 25 times faster in its faster mode. The good results of ROW\u2010PLACE are achieved using\na very effective clustering\u2010based partitioning algorithm in combination with constructive\nmethods that reduce the wire\u2010length of nets involved in terminal propagation.<\/jats:p>","DOI":"10.1155\/1996\/58084","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:06Z","timestamp":1190120226000},"page":"37-48","source":"Crossref","is-referenced-by-count":6,"title":["A Fast Clustering\u2010Based Min\u2010Cut Placement AlgorithmWith Simulated\u2010Annealing Performance"],"prefix":"10.1155","volume":"5","author":[{"given":"Youssef","family":"Saab","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1995,1,30]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1996\/058084.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1996\/58084","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:24:18Z","timestamp":1723202658000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1996\/58084"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,1,30]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1996,1]]}},"alternative-id":["10.1155\/1996\/58084"],"URL":"https:\/\/doi.org\/10.1155\/1996\/58084","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1995,1,30]]}}}