{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:25:45Z","timestamp":1749205545787},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1901,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1996,1]]},"abstract":"<jats:p>This paper presents a router for routing multi\u2010terminal nets in field\u2010programmable gate arrays (FPGAs). The router does not require pre\u2010assignment of routing channels, a phase that is normally accomplished during global routing. This direct routing approach greatly enhances the probability of routing (routability). The multi\u2010terminal routing greatly reduces the total wire length as it approximates a <jats:italic>Steiner tree<\/jats:italic>. The total number of segments required to route the circuits is usually less as compared to other routing approaches. The router has generated excellent routing results for some industrial circuits. The memory requirements for this router are very low. The time needed for the routing is <jats:italic>linear<\/jats:italic> with respect to the size of the circuit.<\/jats:p>","DOI":"10.1155\/1996\/79127","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:50Z","timestamp":1190120210000},"page":"1-10","source":"Crossref","is-referenced-by-count":2,"title":["A Multi\u2010Terminal Net Router for Field\u2010Programmable Gate Arrays"],"prefix":"10.1155","volume":"4","author":[{"given":"Dinesh","family":"Bhatia","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amit","family":"Chowdhary","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1994,10,18]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1996\/079127.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/vlsi\/1996\/079127.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1996\/79127","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T15:21:32Z","timestamp":1723216892000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1996\/79127"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1994,10,18]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1996,1]]}},"alternative-id":["10.1155\/1996\/79127"],"URL":"https:\/\/doi.org\/10.1155\/1996\/79127","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1994,10,18]]}}}