{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T12:10:02Z","timestamp":1723205402233},"reference-count":0,"publisher":"Wiley","issue":"3","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1461,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1996,1]]},"abstract":"<jats:p>In this paper, we discuss the controllability and observability issues in bilateral bit\u2010level systolic arrays. We have introduced a new concept\u2014\u2018<jats:italic>S<\/jats:italic><jats:sub><jats:italic>j<\/jats:italic><\/jats:sub>\u2010controllability in M steps\u2019, which is somewhat analogous to the concept of C\u2010testability and refers to the fact that all the cells in the array can be set to the state <jats:italic>S<\/jats:italic><jats:sub><jats:italic>j<\/jats:italic><\/jats:sub>\n in at most M steps after initialization. Systolic arrays where the value of M is independent of the length, of the array are characterized. Our testing procedure is based on partitioning the array into several identical subarrays which allows us to apply a repetitive pattern of tests and propagate test outcome to the observable extremities so that every cell in the array is tested by a minimum sequence of tests. Based on this concept,we have developed a set of sufficient conditions for an arbitrary bilateral bit\u2010level systolic array to be testable for single faults.<\/jats:p>","DOI":"10.1155\/1996\/84045","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:50Z","timestamp":1190120210000},"page":"257-269","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A Methodology for Testing Arbitrary Bilateral Bit\u2010Level Systolic Arrays"],"prefix":"10.1155","volume":"4","author":[{"given":"S.","family":"Bandyopadhyay","sequence":"first","affiliation":[]},{"given":"A.","family":"Sengupta","sequence":"additional","affiliation":[]},{"given":"B. B.","family":"Bhattacharya","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1996,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1996\/084045.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1996\/84045","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:44:18Z","timestamp":1723203858000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1996\/84045"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1996,1]]},"references-count":0,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1996,1]]}},"alternative-id":["10.1155\/1996\/84045"],"URL":"https:\/\/doi.org\/10.1155\/1996\/84045","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1996,1]]},"assertion":[{"value":"1996-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}