{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T11:05:26Z","timestamp":1740135926465,"version":"3.37.3"},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1095,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["MIP9009239"],"award-info":[{"award-number":["MIP9009239"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1997,1]]},"abstract":"<jats:p>The system\u2010level design process typically involves refining a design specification down to\nthe point where each of the system\u2032s components is described as a block diagram or netlist\nof abstract Register\u2010Transfer (RT) level components. In this paper, we motivate the need for\nsuch a standard RT component set, and describe a library environment that supports automatic\nmodel generation, design reuse, and synthesis with technology\u2010specific estimators. We\ndemonstrate the efficacy of the standard RT\u2010component set approach with experiments performed\non the HLSW92 benchmarks. Our preliminary results indicate only a small overhead\nof about 10% in using these standard, generic components. We then describe an automatic\nmodel generation and technology projection scheme that uses fast (on\u2010line) estimators for\npredicting the area and delay of generic RT components tuned to a particular technology\nlibrary with an accuracy of 10%. These model generators and estimators have been integrated\nwith a high\u2010level synthesis system at U.C. Irvine.<\/jats:p>","DOI":"10.1155\/1997\/35614","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:06Z","timestamp":1190120226000},"page":"155-165","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["RT Component Sets for High\u2010Level Design Applications"],"prefix":"10.1155","volume":"5","author":[{"given":"Nikil D.","family":"Dutt","sequence":"first","affiliation":[]},{"given":"Pradip K.","family":"Jha","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1997,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1997\/035614.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1997\/35614","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T13:26:59Z","timestamp":1723123619000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1997\/35614"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1997,1]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1997,1]]}},"alternative-id":["10.1155\/1997\/35614"],"URL":"https:\/\/doi.org\/10.1155\/1997\/35614","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1997,1]]},"assertion":[{"value":"1997-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}