{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T11:05:10Z","timestamp":1740135910196,"version":"3.37.3"},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1095,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1997,1]]},"abstract":"<jats:p>Submicron feature sizes result in designs in which power density is significantly increased.\nHigh\u2010level synthesis strategies are proposed in this paper to relieve potential thermal problems.\nOperators are placed as close as possible to their data predecessors in order to minimize\nthe interconnection cost while not violating the thermal constraints. Spreading overused\nfunctional units away from the thermal problem area often results in performance degradation.\nIntroducing redundant operators is suggested to reduce the module utilization and hence\nthermal problems among problem modules when system performance is important. Our\nexperimental results show that this technique produces quite satisfactory results for a powerdominated\nexample.<\/jats:p>","DOI":"10.1155\/1997\/39186","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:06Z","timestamp":1190120226000},"page":"183-193","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Taking Thermal Considerations Into Account DuringHigh\u2010Level Synthesis"],"prefix":"10.1155","volume":"5","author":[{"given":"Jen-Pin","family":"Weng","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alice C.","family":"Parker","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1997,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1997\/039186.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1997\/39186","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T13:26:53Z","timestamp":1723123613000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1997\/39186"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1997,1]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1997,1]]}},"alternative-id":["10.1155\/1997\/39186"],"URL":"https:\/\/doi.org\/10.1155\/1997\/39186","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1997,1]]},"assertion":[{"value":"1997-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}