{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T00:02:19Z","timestamp":1723075339439},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1614,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>The layout of a circuit can influence the probability of occurrence of faults. In this\npaper, we develop algorithms that can take advantage of this fact to reduce the chances\nof hard\u2010to\u2010detect (HTD) faults from occurring. We primarily focus on line bridge faults\nin this paper. We define a bridge fault <jats:italic>f<\/jats:italic> as an HTD fault if an automatic test pattern\ngenerator fails to generate a test vector for <jats:italic>f<\/jats:italic> in a reasonable amount of CPU\u2010time. It is\ncommon practice to drop such HTD faults from consideration during test generation.\nThe chip fault coverage achieved by a test set is poor if the fault set consists of many\nHTD faults. We can combat this problem by avoiding altogether, or by reducing the\nprobability of, the occurrence of HTD faults. In this paper, we consider hard\u2010to\u2010detect\nbridging faults and show how module placement rules can be derived to reduce the\nprobability of these faults. A genetic placement algorithm that optimizes area while\nrespecting these rules is presented. The placement algorithm has been implemented for\nstandard\u2010cell layout style on a SUN\/SPARC and tested against several sample circuits.<\/jats:p>","DOI":"10.1155\/1998\/10193","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"347-352","source":"Crossref","is-referenced-by-count":0,"title":["Testability\u2010Driven Layout of Combinational Circuits"],"prefix":"10.1155","volume":"7","author":[{"given":"C. P.","family":"Ravikumar","sequence":"first","affiliation":[]},{"given":"Nikhil","family":"Sharma","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1995,8]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/010193.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/10193","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T23:01:56Z","timestamp":1723071716000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/10193"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,8]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/10193"],"URL":"https:\/\/doi.org\/10.1155\/1998\/10193","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1995,8]]}}}