{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T00:02:19Z","timestamp":1723075339093},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1223,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>A codesign methodology is proposed which is suitable for control\u2010dominated systems\nbut can also be extended to more complex ones. Its main purpose is to optimize the\ntrade\u2010off between hardware performance and software reprogrammability and\nreconfigurability. The methodology proposed intends to cover the development of the\nwhole system. It deals in greater detail with the steps that can be made without the need\nfor any particular assumption regarding the target architecture. These steps concern\nsplitting up the specification of the system into a set of individually synthesizable\nelements, and then grouping them for the subsequent mapping stage. In order to\ndecrease the complexity of each partitioning attempt, a two step algorithm is proposed,\nthus permitting a wide exploration of possible solutions. The methodology is based on\nthe TTL language, an extension of the T\u2010LOTOS Formal Description Technique which\nprovides a large amount of operators as well as a formal basis. Finally, an example\npointing out the complete design cycle, excepting the allocation stage is provided.<\/jats:p>","DOI":"10.1155\/1998\/18340","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"401-423","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Formal Codesign Methodology with Multistep Partitioning"],"prefix":"10.1155","volume":"7","author":[{"given":"Vincenza","family":"Carchiolo","sequence":"first","affiliation":[]},{"given":"Michele","family":"Malgeri","sequence":"additional","affiliation":[]},{"given":"Giuseppe","family":"Mangioni","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1996,8,26]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/018340.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/18340","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T23:01:55Z","timestamp":1723071715000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/18340"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1996,8,26]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/18340"],"URL":"https:\/\/doi.org\/10.1155\/1998\/18340","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1996,8,26]]},"assertion":[{"value":"1996-02-22","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1996-08-26","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1996-08-26","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}