{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,10]],"date-time":"2024-08-10T00:02:28Z","timestamp":1723248148970},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":730,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"name":"Texas Advanced Research Program","award":["003658459"],"award-info":[{"award-number":["003658459"]}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>With the increasing density of VLSI circuits, the interconnection wires are getting\npacked even closer. This has increased the effect of interaction between these wires on\ncircuit performance and hence, the importance of controlling crosstalk. We consider the\ngridded channel routing problem where, specifically, the channel has 3 routing layers in\nthe <jats:italic>VHV<\/jats:italic> configuration. Given a horizontal track assignment for the nets, we present an\noptimal algorithm for minimizing the crosstalk between vertical wiring segments in the\nchannel by finding an optimal vertical layer assignment for them. We give an algorithm\nthat minimizes total crosstalk between vertical wires on the same <jats:italic>V<\/jats:italic> layer on adjacent\ncolumns of the grid in <jats:italic>O<\/jats:italic>(\u03bd log\u03bd) time using <jats:italic>O<\/jats:italic>(\u03bd) memory, where the channel has \u03bd\ncolumns. We then extend this algorithm to consider crosstalk between wires in nonadjacent\ncolumns and between wires on different layers. Finally, we show how our\nalgorithms can be extended to take crosstalk tolerance specifications for nets into\naccount.<\/jats:p>","DOI":"10.1155\/1998\/34910","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"73-84","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Minimum Crosstalk Vertical Layer Assignment for Three\u2010Layer VHV Channel Routing"],"prefix":"10.1155","volume":"7","author":[{"given":"Shashidhar","family":"Thakur","sequence":"first","affiliation":[]},{"given":"Kai-Yuan","family":"Chao","sequence":"additional","affiliation":[]},{"given":"D. F.","family":"Wong","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1998,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/034910.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/34910","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T15:22:47Z","timestamp":1723216967000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/34910"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,1]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/34910"],"URL":"https:\/\/doi.org\/10.1155\/1998\/34910","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,1]]},"assertion":[{"value":"1998-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}