{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T11:05:27Z","timestamp":1740135927134,"version":"3.37.3"},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1544,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/100000006","name":"Office of Naval Research","doi-asserted-by":"publisher","award":["N000149410462"],"award-info":[{"award-number":["N000149410462"]}],"id":[{"id":"10.13039\/100000006","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>A technique for designing totally self\u2010checking (TSC) FCMOS (Fully Complementary\nMOS) designs for multiple faults is presented in this paper. The existing techniques for\nself checking design consider only single faults, and suffer from high silicon area\noverhead. The multiple faults considered in this paper are multiple breaks, multiple\ntransistors stuck\u2010offs and multiple transistors stuck\u2010ons. Starting from FCMOS design,\nsmall modifications (addition of two\u2010weak transistors) make the original circuit totally\nself\u2010checking. Experiemntal results show the overhead, delay and power consumption\nfor the proposed technique. This paper also presents a technique for designing\nmultistage TSC FCMOS circuits.<\/jats:p>","DOI":"10.1155\/1998\/37237","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"151-161","source":"Crossref","is-referenced-by-count":2,"title":["On Self\u2010Checking Design of CMOS Circuits for Multiple Faults"],"prefix":"10.1155","volume":"7","author":[{"given":"Fadi","family":"Busaba","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Parag K.","family":"Lala","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alvernon","family":"Walker","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1995,10,10]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/037237.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/37237","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:40:22Z","timestamp":1723070422000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/37237"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,10,10]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/37237"],"URL":"https:\/\/doi.org\/10.1155\/1998\/37237","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1995,10,10]]}}}