{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T10:40:02Z","timestamp":1723200002611},"reference-count":0,"publisher":"Wiley","issue":"1-4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":730,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>Electron transport properties of strained\u2010Si on relaxed Si<jats:sub>1 \u2013 x<\/jats:sub>Ge<jats:sub>x<\/jats:sub> channel MOSFETs have been studied using a Monte Carlo simulator. The steady\u2010 and non\u2010steady\u2010state\nhigh\u2010longitudinal field transport regimes have been described in detail. Electronvelocity\u2010\novershoot effects are studied in deep\u2010submicron strained\u2010Si MOSFETs, where\nthey show an improvement over the performance of their normal silicon counterparts.\nThe impact of the Si layer strain on the performance enhancement are described in\ndepth in terms of microscopic magnitudes.<\/jats:p>","DOI":"10.1155\/1998\/48528","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:07Z","timestamp":1190120287000},"page":"253-256","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Monte Carlo Simulation of Non\u2010Local Transport Effectsin Strained Si on Relaxed Si<sub>1 \u2013 x<\/sub>Ge<sub>x<\/sub> Heterostructures"],"prefix":"10.1155","volume":"8","author":[{"given":"F.","family":"G\u00e1miz","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J. B.","family":"Rold\u00e1n","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J. A.","family":"L\u00f3pez-Villanueva","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1998,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/048528.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/48528","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T10:00:14Z","timestamp":1723197614000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/48528"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,1]]},"references-count":0,"journal-issue":{"issue":"1-4","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/48528"],"URL":"https:\/\/doi.org\/10.1155\/1998\/48528","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,1]]},"assertion":[{"value":"1998-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}