{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T11:04:59Z","timestamp":1740135899895,"version":"3.37.3"},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":730,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["MIP-9409905"],"award-info":[{"award-number":["MIP-9409905"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>We consider the problem of selecting the proper <jats:italic>implementation<\/jats:italic> of each circuit <jats:italic>module<\/jats:italic>\nfrom a cell library to minimize the propagation delay along every path from any <jats:italic>primary input<\/jats:italic> to any <jats:italic>primary output<\/jats:italic> subject to an upper bound on the total area of the circuit.\nDifferent module implementations may have different areas and delays on the paths. Wc\nshow that the latter problem is NP\u2010hard even for directed acyclic graphs with two\nimplementations per module and no restrictions on the overall area of the circuit. Wc\npresent a novel retiming based heuristic for determining the minimum clock period on\n<jats:italic>sequential circuits<\/jats:italic>. Although our heuristics may handle a bound on the total area of the\ncircuit, emphasis is given on the timing issue.<\/jats:p>","DOI":"10.1155\/1998\/49145","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"211-224","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Timing\u2010Driven Circuit Implementation"],"prefix":"10.1155","volume":"7","author":[{"given":"Dimitrios","family":"Karayiannis","sequence":"first","affiliation":[]},{"given":"Spyros","family":"Tragoudas","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1998,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/049145.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/49145","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:40:31Z","timestamp":1723070431000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/49145"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,1]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/49145"],"URL":"https:\/\/doi.org\/10.1155\/1998\/49145","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,1]]},"assertion":[{"value":"1996-02-29","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1998-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}