{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,20]],"date-time":"2025-07-20T04:28:34Z","timestamp":1752985714581},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1656,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>This work examines the complexity of scheduling for high level synthesis. It has been\nshown that the problem of finding the minimum time schedule for a set of chains of\noperations of two types using two processors, one of each type, is NP\u2010complete.\nHowever, for two chains only, a polynomial time algorithm can been obtained for\nscheduling with two processors. The problem of scheduling a rooted binary tree of two\noperation types on two processors, one of each type, has been shown to be NP\u2010complete.\nIt has also been proved that absolute approximations for schedule length\nminimization or processor minimization are NP\u2010complete. A related resource\nconstrained scheduling problem has also been shown to be NP\u2010hard.<\/jats:p>","DOI":"10.1155\/1998\/52807","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"337-346","source":"Crossref","is-referenced-by-count":8,"title":["Complexity of Scheduling in High Level Synthesis"],"prefix":"10.1155","volume":"7","author":[{"given":"C. A.","family":"Mandal","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P. P.","family":"Chakrabarti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Ghose","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1995,6,20]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/052807.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/52807","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T23:01:54Z","timestamp":1723071714000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/52807"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,6,20]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/52807"],"URL":"https:\/\/doi.org\/10.1155\/1998\/52807","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1995,6,20]]}}}