{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T00:04:31Z","timestamp":1723075471321},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1636,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>In FPGAs the routing resources are fixed and their usage is constrained by the location\nof antifuses. In addition, the antifuses affect the layout performance significantly,\ndepending on the technology. Hence, simplistic placement level assumptions turn out to\nbe grossly inadequate in predicting the timing and wirability behavior of a layout.\nThere is a need, therefore, for a layout technique which changes the layout at placement\nlevel based on accurate post\u2010layout timing analysis and net wirability. In this paper we\nconsider such a wirability and performance driven layout flow for row\u2010based FPGAs.\nTiming information from a post\u2010layout timing analyzer and wirability information\nfrom global and channel routers are used by an incremental placer to effectively perturb\nthe placement. A large improvement (up to 29%) in timing, has been obtained\n(compared to non\u2010iterative FPGA layout) for a set of industrial designs and benchmark\nexamples.<\/jats:p>","DOI":"10.1155\/1998\/57380","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"353-364","source":"Crossref","is-referenced-by-count":0,"title":["Performance and Wirability Driven Layout for Row\u2010Based FPGAs"],"prefix":"10.1155","volume":"7","author":[{"given":"Sudip","family":"Nag","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kaushik","family":"Roy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1995,7,10]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/057380.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/57380","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T23:01:51Z","timestamp":1723071711000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/57380"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,7,10]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/57380"],"URL":"https:\/\/doi.org\/10.1155\/1998\/57380","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1995,7,10]]}}}