{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T10:40:02Z","timestamp":1723200002560},"reference-count":0,"publisher":"Wiley","issue":"1-4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":730,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>The design of Monte Carlo FET simulations is discussed, with specific attention to the methods used to describe quantum confinement effects. A new model is presented, which employs self\u2010consistent coupling of Schrodinger, Poisson and Monte Carlo algorithms, and explicit calculation of the scattering rates between confined and unconfined states. Comparisons between the new model and a standard semi\u2010classical Monte Carlo model are presented for a 0.1 \u03bcm gate\u2010length In<jats:sub>0.52<\/jats:sub>Al<jats:sub>0.48<\/jats:sub>As\/In<jats:sub>0.53<\/jats:sub> Ga<jats:sub>0.47<\/jats:sub>As\/InP MODFET. Whilst the quantum model yields minor corrections in the predicted output characteristics, it is found that these results can be achieved without repeated iterations of the Schrodinger equation.<\/jats:p>","DOI":"10.1155\/1998\/57936","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:07Z","timestamp":1190120287000},"page":"21-27","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Inclusion of Quantum Confinement Effects in Self\u2010Consistent Monte Carlo Device Simulations"],"prefix":"10.1155","volume":"8","author":[{"given":"R. W.","family":"Kelsall","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A. J.","family":"Lidsey","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1998,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/057936.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/57936","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T10:01:39Z","timestamp":1723197699000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/57936"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,1]]},"references-count":0,"journal-issue":{"issue":"1-4","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/57936"],"URL":"https:\/\/doi.org\/10.1155\/1998\/57936","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,1]]},"assertion":[{"value":"1998-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}