{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,10]],"date-time":"2024-08-10T00:02:25Z","timestamp":1723248145781},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":730,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["MIP-9409905"],"award-info":[{"award-number":["MIP-9409905"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>In recent years there has been an extensive interest in clustering the modules of a\nnetwork so that the maximum delay from any <jats:italic>primary input<\/jats:italic> to any <jats:italic>primary<\/jats:italic> output is\nminimized [8, 7, 6]. Clusters have a maximum capacity and modules may have different\nimplementations. All existing CAD frameworks initially select an implementation of\neach module, and at a later stage they cluster the modules. We present an approach that\nclusters the nodes, while considering their alternative implementations, so that we\nfurther minimize the maximum delay after the clustering. Our approach is based on\noptimal algorithms for restricted versions of this complex problem in circuit design, and\noutperforms the conventional approach, which first obtains an implementation for each\ncircuit module without considering clustering and then, in a later step, performs\nclustering.<\/jats:p>","DOI":"10.1155\/1998\/69289","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"1-13","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Clustering Network Modules with Different Implementations for Delay Minimization"],"prefix":"10.1155","volume":"7","author":[{"given":"Dimitrios","family":"Karayiannis","sequence":"first","affiliation":[]},{"given":"Spyros","family":"Tragoudas","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1998,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/069289.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/69289","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T15:22:51Z","timestamp":1723216971000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/69289"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,1]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/69289"],"URL":"https:\/\/doi.org\/10.1155\/1998\/69289","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,1]]},"assertion":[{"value":"1998-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}