{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T11:42:21Z","timestamp":1743507741267},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":730,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["MIP-9208165"],"award-info":[{"award-number":["MIP-9208165"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["MIP-9423886"],"award-info":[{"award-number":["MIP-9423886"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003593","name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","doi-asserted-by":"publisher","award":["200484\/89.3"],"award-info":[{"award-number":["200484\/89.3"]}],"id":[{"id":"10.13039\/501100003593","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000183","name":"Army Research Office","doi-asserted-by":"publisher","award":["DAAH04-93-G-0323"],"award-info":[{"award-number":["DAAH04-93-G-0323"]}],"id":[{"id":"10.13039\/100000183","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>In this paper a top\u2010down methodology is presented for synthesizing clock distribution\nnetworks based on application\u2010dependent localized clock skew. The methodology is\ndivided into four phases: 1) determination of an optimal clock skew schedule for\nimproving circuit performance and reliability; 2) design of the topology of the clock tree\nbased on the circuit hierarchy and minimum clock path delays; 3) design of circuit\nstructures to implement the delay values associated with the branches of the clock tree;\nand 4) design of the geometric layout of the clock distribution network. Algorithms to\ndetermine an optimal clock skew schedule, the optimal clock delay to each register, the\nnetwork topology, and the buffer circuit dimensions are presented.<\/jats:p><jats:p>The clock distribution network is implemented at the circuit level in CMOS\ntechnology and a design strategy based on this technology is presented to implement the\nindividual branch delays. The minimum number of inverters required to implement the\nbranch delays is determined, while preserving the polarity of the clock signal. The clock\nlines are transformed from distributed resistive\u2010capacitive interconnect lines into purely\ncapacitive interconnect lines by partitioning the RC interconnect lines with inverting\nrepeaters. The inverters are specified by the geometric size of the transistors, the slope of\nthe ramp shaped input\/output waveform, and the output load capacitance. The branch\ndelay model integrates an inverter delay model with an interconnect delay model.\nMaximum errors of less than 2.5% for the delay of the clock paths and 4% for the clock\nskew between any two registers belonging to the same global data path are obtained as\ncompared with SPICE Level\u20103.<\/jats:p>","DOI":"10.1155\/1998\/72951","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"31-57","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Automated Synthesis of Skew\u2010Based Clock Distribution Networks"],"prefix":"10.1155","volume":"7","author":[{"given":"Jos\u00e9 Luis","family":"Neves","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eby G.","family":"Friedman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1998,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/072951.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/72951","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T15:22:41Z","timestamp":1723216961000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/72951"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,1]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/72951"],"URL":"https:\/\/doi.org\/10.1155\/1998\/72951","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,1]]},"assertion":[{"value":"1998-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}