{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,10]],"date-time":"2024-08-10T00:02:28Z","timestamp":1723248148435},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":730,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["MIP 949119"],"award-info":[{"award-number":["MIP 949119"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>The synthesis of the power distribution network is an important problem in the layout\ndesign of VLSI systems. In this paper we propose novel methods to solve the problem of\ndesigning minimal area power distribution nets, while satisfying voltage drop and\nelectromigration constraints. We will see that our methods significantly improve upon\ncurrent techniques. We propose two novel greedy heuristics for power net design\u2010one\nbased on bottom\u2010up tree construction using greedy merging and the other based on top\u2010down\nlinearly separable partitioning. We test the efficacy of our techniques on\nbenchmark instances. The areas required by our methods on typical instances are\nsignificantly smaller than those obtained using previous methods.<\/jats:p>","DOI":"10.1155\/1998\/76525","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"59-72","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Power Distribution Synthesis for VLSI"],"prefix":"10.1155","volume":"7","author":[{"given":"Ashok","family":"Vittal","sequence":"first","affiliation":[]},{"given":"Malgorzata","family":"Marek-Sadowska","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1998,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/076525.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/76525","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T15:22:44Z","timestamp":1723216964000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/76525"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,1]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/76525"],"URL":"https:\/\/doi.org\/10.1155\/1998\/76525","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,1]]},"assertion":[{"value":"1998-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}