{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T23:40:02Z","timestamp":1723074002233},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":730,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>A common technique widely used to achieve fault tolerance in systolic arrays consists in\nincorporating in the array additional processing elements (PEs) and extra bypass links.\nGiven a sufficient number of PEs and a large enough set of bypass links, it might seem\nthat the array can easily tolerate a large number of faults provided they do not occur in\nconsecutive locations. It is not always the case as shown in this paper. In fact, certain\nfault patterns exist and may occur which would prevent any kind of restructuring of the\naray, thus making the structure unusable. For a given set of bypass links from each PE\nin the array, it is possible to identify such fault patterns which will prevent any\nreconfiguration. In this paper, we identify the class of fault patterns that are\ncatastrophic for linear systolic arrays, examine their characteristics, and describe a\nmethod for constructing such fault patterns.<\/jats:p>","DOI":"10.1155\/1998\/79841","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"143-150","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Characterization of Catastrophic Faults in Reconfigurable Systolic Arrays"],"prefix":"10.1155","volume":"7","author":[{"given":"Vincenzo","family":"Acciaro","sequence":"first","affiliation":[]},{"given":"Amiya","family":"Nayak","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1998,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/079841.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/79841","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:40:33Z","timestamp":1723070433000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/79841"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,1]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/79841"],"URL":"https:\/\/doi.org\/10.1155\/1998\/79841","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,1]]},"assertion":[{"value":"1996-02-26","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1998-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}