{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,24]],"date-time":"2025-03-24T06:55:20Z","timestamp":1742799320377},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":730,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/501100002488","name":"Hannam University","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002488","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>The inter\u2010wire spacing in a VLSI chip becomes closer as the VLSI fabrication\ntechnology rapidly evolves. Accordingly, it becomes important to minimize crosstalk\ncaused by the coupling capacitance between adjacent wires in the layout design for the\nfast and safe VLSI circuits. We present a simulated annealing approach based on\nsegment rearrangement to crosstalk minimization in an initially gridded channel\nrouting. The proposed technique is compared with previous track\u2010oriented techniques,\nespecially a track permutation technique whose performance is bounded by an\nexhaustive track permutation algorithm. Experiments showed that the presented\ntechnique is more effective than the track permutation technique.<\/jats:p>","DOI":"10.1155\/1998\/81296","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"85-95","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Simulated Annealing Approach to Crosstalk Minimization in Gridded Channel Routing"],"prefix":"10.1155","volume":"7","author":[{"given":"Kyoung-Son","family":"Jhang","sequence":"first","affiliation":[]},{"given":"Soonhoi","family":"Ha","sequence":"additional","affiliation":[]},{"given":"Chu Shik","family":"Jhon","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1998,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/081296.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/81296","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T15:22:36Z","timestamp":1723216956000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/81296"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,1]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/81296"],"URL":"https:\/\/doi.org\/10.1155\/1998\/81296","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,1]]},"assertion":[{"value":"1998-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}