{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T12:10:01Z","timestamp":1723205401544},"reference-count":0,"publisher":"Wiley","issue":"1-4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":730,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>Topologically rectangular grids offer simplicity and efficiency in the design of parallel semiconductor\ndevice simulators tailored for mesh connected MIMD platforms. This paper\npresents several approaches to the generation of topologically rectangular 2D and 3D grids.\nThe effects of the partitioning of such grids on different processor configurations are studied.\nA simulated annealing algorithm is used to optimise the partitioning of 2D and 3D grids on\ntwo dimensional arrays of processors. Problems related to the discretization, parallel matrix\ngeneration and solution strategy are discussed. The use of topologically rectangular grids is\nillustrated through the example of power electronic device simulation.<\/jats:p>","DOI":"10.1155\/1998\/82084","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:27Z","timestamp":1190120247000},"page":"91-95","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Topologically Rectangular Grids in the Parallel Simulationof Semiconductor Devices"],"prefix":"10.1155","volume":"6","author":[{"given":"A.","family":"Asenov","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A. R.","family":"Brown","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Roy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J. R.","family":"Barker","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1998,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/082084.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/82084","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:34:01Z","timestamp":1723203241000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/82084"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,1]]},"references-count":0,"journal-issue":{"issue":"1-4","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/82084"],"URL":"https:\/\/doi.org\/10.1155\/1998\/82084","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,1]]},"assertion":[{"value":"1998-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}