{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T23:40:02Z","timestamp":1723074002510},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":730,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>Fault sets that accurately describe physical failures are required for efficient pattern\ngeneration and fault coverage evaluation. The fault model presented in this paper\nuniquely describes all structural changes in the transistor net list that can be caused by\nspot defects, including bridging faults that connect more than two nets, break faults that\nbreak a net into more than two parts, and compound faults. The developed analysis\nmethod extracts the comprehensive set of realistic faults from the layout of CMOS ICs\nand for each fault computes the probability of occurrence. The results obtained by the\ntool REFLEX show that bridging faults connecting more than two nets account for a\nsignificant portion of all faults and cannot be neglected.<\/jats:p>","DOI":"10.1155\/1998\/83615","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"163-176","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Realistic Fault Modeling and Extraction of Multiple Bridging and Break Faults"],"prefix":"10.1155","volume":"7","author":[{"given":"Gerald","family":"Spiegel","sequence":"first","affiliation":[]},{"given":"Albrecht P.","family":"Stroele","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1998,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/083615.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/83615","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:40:28Z","timestamp":1723070428000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/83615"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,1]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/83615"],"URL":"https:\/\/doi.org\/10.1155\/1998\/83615","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,1]]},"assertion":[{"value":"1996-08-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1998-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}