{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T11:05:27Z","timestamp":1740135927143,"version":"3.37.3"},"reference-count":0,"publisher":"Wiley","issue":"3","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":730,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"name":"US Air Force","award":["F33615-9 l-C- 1811","7056","J-FBI-89-094"],"award-info":[{"award-number":["F33615-9 l-C- 1811","7056","J-FBI-89-094"]}]},{"DOI":"10.13039\/100009224","name":"Advanced Research Projects Agency","doi-asserted-by":"publisher","award":["F33615-9 l-C- 1811","7056","J-FBI-89-094"],"award-info":[{"award-number":["F33615-9 l-C- 1811","7056","J-FBI-89-094"]}],"id":[{"id":"10.13039\/100009224","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100012473","name":"Federal Bureau of Investigation","doi-asserted-by":"publisher","award":["F33615-9 l-C- 1811","7056","J-FBI-89-094"],"award-info":[{"award-number":["F33615-9 l-C- 1811","7056","J-FBI-89-094"]}],"id":[{"id":"10.13039\/100012473","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>High level synthesis is the process of generating register transfer (RT) level designs from\nbehavioral specifications. High level synthesis systems have traditionally taken into\naccount such constraints as area, clock period and throughput time. Many high level\nsynthesis systems [1] permit generation of many alternative RT level designs meeting\nthese constraints in a relatively short time. If it is possible to accurately estimate the\npower consumption of RT level designs, then a low power design from among these\nalternatives can be selected.<\/jats:p><jats:p>In this paper, we present an accurate power estimation technique for register transfer\nlevel designs generated by high level synthesis systems. The technique has four main\naspects: (1) Each RT level component used in high level synthesis is characterized for\naverage switched capacitance per input vector. This data is stored in the RT level\ncomponent library. (2) Using user\u2010specified stimuli, the given behavioral description is\nsimulated and event activities of various operators and carriers are measured. Then, the\nbehavioral specification is submitted to the synthesis system and a number of alternative\nRTL designs meeting speed, space and throughput rate constraints are generated. (3)\nEvent activity of each component in an RT level design is estimated using the event\nactivities measured at the time of behavior level profiling and the structure of the RTL\ndesign itself. (4) The event activities so obtained are then used to modulate the average\nswitched capacitances of the respective RT level components to obtain an estimate the\ntotal switched capacitance of each component.<\/jats:p><jats:p>Detailed power estimation procedures for the three different parts of RTL designs,\nnamely, data path, controller and interconnect are presented. Experimental results\nobtained from a variety of designs show that the power estimates are within 3%\u201310%\nof the actual power measured by simulating the transistor level designs extracted from\nmask layouts.<\/jats:p>","DOI":"10.1155\/1998\/93106","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"255-270","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["Architectural Power Estimation Based on Behavior Level Profiling"],"prefix":"10.1155","volume":"7","author":[{"given":"Srinivas","family":"Katkoori","sequence":"first","affiliation":[]},{"given":"Ranga","family":"Vemuri","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1998,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/093106.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/93106","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:53:52Z","timestamp":1723071232000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/93106"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,1]]},"references-count":0,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/93106"],"URL":"https:\/\/doi.org\/10.1155\/1998\/93106","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,1]]},"assertion":[{"value":"1998-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}