{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T00:02:18Z","timestamp":1723075338735},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1758,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>We present a VLSI synthesis environment dedicated to the design of image processing architectures. The environment includes a \u201cfront\u2010end\u201d data\u2010flow emulator for validation of the algorithms and the RTL\u2010synthesis system called ALPHA. The latter implements a stochastic search in the design space and produces efficient solutions considering the \u201crestricted\u201d domain of concerned applications. Two simulated Annealing (SA) algorithms run in sequence for data\u2010path synthesis (scheduling and module selection) and then for control synthesis and data\u2010path completion (binding). An interesting feature of the first optimization is the use of the data\u2010flow graph regularity to predict the control influence in terms of the future design. A few designs have already been compiled under this environment including a default detector presented here.<\/jats:p>","DOI":"10.1155\/1998\/95421","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"321-336","source":"Crossref","is-referenced-by-count":2,"title":["A High Level Synthesis System for VLSI Image Processing Applications"],"prefix":"10.1155","volume":"7","author":[{"given":"Fran\u00e7ois S.","family":"Verdier","sequence":"first","affiliation":[]},{"given":"Bertrand","family":"Zavidovique","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1995,3,10]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/095421.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/95421","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T23:01:48Z","timestamp":1723071708000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/95421"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,3,10]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/95421"],"URL":"https:\/\/doi.org\/10.1155\/1998\/95421","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1995,3,10]]}}}