{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T06:24:38Z","timestamp":1747895078160,"version":"3.37.3"},"reference-count":0,"publisher":"Wiley","issue":"3","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":730,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["MIP-9308426"],"award-info":[{"award-number":["MIP-9308426"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1998,1]]},"abstract":"<jats:p>We propose a logic synthesis system that includes power optimization <jats:italic>after<\/jats:italic> technology\nmapping. Our approach is unique in that our post\u2010mapping logic transformations take\ninto account information on circuit delay, capacitance, arrival times, glitches, etc., to\nprovide much better accuracy than previously proposed technology\u2010independent power\noptimization methods. By changing connections in a mapped circuit, we achieve power\nimprovements up to 13% in case of area\u2010 or delay\u2010optimized circuits, with reductions\nalso in area and delay. We show that by applying the proposed technique on circuits\nthat are already restructured for lower switching activity using the technique presented\nin [11], total power savings up to 59% in case of area\u2010optimized circuits and 38% in case\nof delay\u2010optimized circuits are achievable. The post\u2010mapping transformations are based\non the <jats:italic>transition density<\/jats:italic> model of circuit switching activity and the concept of\n<jats:italic>permissible logic functions<\/jats:italic>. The techniques presented here are applicable equally well to\nboth synchronous and asynchronous circuits. The power measurements are done under\na general delay model.<\/jats:p>","DOI":"10.1155\/1998\/96768","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:57:36Z","timestamp":1190120256000},"page":"289-301","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Post\u2010Mapping Transformations for Low\u2010Power Synthesis"],"prefix":"10.1155","volume":"7","author":[{"given":"Rajendran","family":"Panda","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Farid N.","family":"Najm","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1998,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1998\/096768.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1998\/96768","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:53:56Z","timestamp":1723071236000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1998\/96768"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,1]]},"references-count":0,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1998,1]]}},"alternative-id":["10.1155\/1998\/96768"],"URL":"https:\/\/doi.org\/10.1155\/1998\/96768","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,1]]},"assertion":[{"value":"1998-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}