{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T10:10:01Z","timestamp":1723198201939},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":365,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1999,1]]},"abstract":"<jats:p>This paper reviews proposals for extensions to VHDL to support high\u2010level modeling\nand places them within a taxonomy that describes the modeling requirements they\naddress. Many of the proposals focus on object\u2010oriented extensions, whereas this paper\nargues that extension of VHDL to support high\u2010level modeling requires a broader\nreview. The paper presents a detailed discussion of issues to be considered in adding\nhigh\u2010level modeling extensions to VHDL, including concurrency and communication,\nabstraction using entity interfaces, object\u2010oriented data modeling, encapsulation, signal\nassignment semantics, shared variables, multiple inheritance, genericity and synthesis.\nEmphasis is placed on the importance of designing simple orthogonal semantic\nmechanisms that interact in well defined ways, and that integrate cleanly with existing\nlanguage features.<\/jats:p>","DOI":"10.1155\/1999\/20186","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:37Z","timestamp":1190120317000},"page":"217-235","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Principles for Language Extensions to VHDL to Support High\u2010Level Modeling"],"prefix":"10.1155","volume":"10","author":[{"given":"Peter J.","family":"Ashenden","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philip A.","family":"Wilsey","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1999,3,22]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1999\/020186.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1999\/20186","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T09:49:15Z","timestamp":1723196955000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1999\/20186"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,1]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1999,1]]}},"alternative-id":["10.1155\/1999\/20186"],"URL":"https:\/\/doi.org\/10.1155\/1999\/20186","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1999,1]]},"assertion":[{"value":"1997-11-09","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-03-22","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-03-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}