{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T12:10:02Z","timestamp":1723205402405},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":365,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1999,1]]},"abstract":"<jats:p>Most algorithms for reconfigurable meshes (R\u2010meshes) are based on the divide\u2010and\u2010conquer\n(DAC) strategy. Although the strategy <jats:italic>per se<\/jats:italic> does not require the subproblems\nto be equal in size, existing DAC algorithms for R\u2010meshes do divide the problem\napproximately evenly. This paper demonstrates that dividing a problem <jats:italic>evenly<\/jats:italic> is not\nnecessarily a good way to decompose a problem. There are occasions on which an\n<jats:italic>irregular decomposition scheme<\/jats:italic> may be preferable. We take this approach and obtain a\nnew sorting algorithm. Our sorting algorithm has several strengths: it is simple, scalable,\nand as broadcast\u2010efficient as the best known result.<\/jats:p>","DOI":"10.1155\/1999\/25362","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:21Z","timestamp":1190120301000},"page":"1-16","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Sorting on Reconfigurable Meshes:An Irregular Decomposition Approach"],"prefix":"10.1155","volume":"9","author":[{"given":"Ten H.","family":"Lai","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ming-Jye","family":"Sheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1999,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1999\/025362.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/vlsi\/1999\/025362.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1999\/25362","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:52:07Z","timestamp":1723204327000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1999\/25362"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,1]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1999,1]]}},"alternative-id":["10.1155\/1999\/25362"],"URL":"https:\/\/doi.org\/10.1155\/1999\/25362","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1999,1]]},"assertion":[{"value":"1997-05-05","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-01-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}