{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T09:05:33Z","timestamp":1747904733946},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":407,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1999,1]]},"abstract":"<jats:p><jats:italic>Interconnect tuning<\/jats:italic> is an increasingly critical degree of freedom in the physical design of\nhigh\u2010performance VLSI systems. By interconnect tuning, we refer to the selection of line\nthicknesses, widths and spacings in multi\u2010layer interconnect to simultaneously optimize\nsignal distribution, signal performance, signal integrity, and interconnect manufacturability\nand reliability. This is a key activity in most leading\u2010edge design projects, but has\nreceived little attention in the literature. Our work provides the first technology\u2010specific\nstudies of interconnect tuning in the literature. We center on global wiring layers and\ninterconnect tuning issues related to bus routing, repeater insertion, and choice of\nshielding\/spacing rules for signal integrity and performance. We address four basic\nquestions. (1) How should width and spacing be allocated to maximize performance for\na given line pitch? (2) For a given line pitch, what criteria affect the optimal interval at\nwhich repeaters Should be inserted into global interconnects? (3) Under what circumstances\nare shield wires the optimum technique for improving interconnect performance?\n(4) In global interconnect with repeaters, what other interconnect tuning is possible?\nOur study of question (4) demonstrates a new approach of offsetting repeater placements\nthat can reduce worst\u2010case cross\u2010chip delays by over 30% in current technologies.<\/jats:p>","DOI":"10.1155\/1999\/38974","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:37Z","timestamp":1190120317000},"page":"21-34","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":16,"title":["Tuning Strategies for Global Interconnectsin High\u2010Performance Deep\u2010Submicron ICs"],"prefix":"10.1155","volume":"10","author":[{"given":"Andrew B.","family":"Kahng","sequence":"first","affiliation":[]},{"given":"Sudhakar","family":"Muddu","sequence":"additional","affiliation":[]},{"given":"Egino","family":"Sarto","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1998,11,20]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1999\/038974.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/vlsi\/1999\/038974.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1999\/38974","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T15:17:47Z","timestamp":1723216667000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1999\/38974"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,11,20]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1999,1]]}},"alternative-id":["10.1155\/1999\/38974"],"URL":"https:\/\/doi.org\/10.1155\/1999\/38974","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,11,20]]},"assertion":[{"value":"1998-09-07","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1998-11-20","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1998-11-20","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}