{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,10]],"date-time":"2024-08-10T00:02:28Z","timestamp":1723248148153},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":407,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1999,1]]},"abstract":"<jats:p>Traditional placement problems are studied under a fully specified cell library and a\ncomplete netlist. However, in the first, <jats:italic>e.g.<\/jats:italic>, 2 years of a 2 \u2013 3 year microprocessor design\ncycle, the detailed netlist is unavailable. For area and performance estimation, layout\nmust nevertheless be done with incomplete information. Another source of incompleteness\ncomes from logic synthesis changes; some instances and their parameters will change\nas the project evolves. In the re\u2010configurable computing area, sometimes we need to\nperform quick placement before all information is available. The problem of placement\nwith incomplete data (PID) can be abstracted as having to place a circuit when <jats:italic>p<\/jats:italic><jats:sub><jats:italic>c<\/jats:italic><\/jats:sub><jats:italic>%<\/jats:italic> of the cells and <jats:italic>p<\/jats:italic><jats:sub><jats:italic>n<\/jats:italic><\/jats:sub><jats:italic>%<\/jats:italic> of the nets are missing. The key challenge in PID is how to add missing\ncells and nets.<\/jats:p><jats:p>In this paper, two \u201cpatching\u2010methods\u201d for adding missing nets and cells are proposed.\nThe methods are called <jats:italic>abstraction<\/jats:italic> and <jats:italic>fusion<\/jats:italic>.<\/jats:p><jats:p>Experimental results are very interesting. First, they show that PID is a difficult problem\nand an arbitrary (and perhaps intuitively sound) method may not produce highquality\nresults. Experiments verify that the abstraction method is a very good predictor\nand that fusion is not. Specifically, when a circuit has 10% incompleteness, abstraction\ncan predict the final total wirelength with an error of 5.8% while fusion has a 67.8% error\nin predicting the wirelength in the same circuit.<\/jats:p>","DOI":"10.1155\/1999\/42648","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:37Z","timestamp":1190120317000},"page":"57-70","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Placement with Incomplete Data"],"prefix":"10.1155","volume":"10","author":[{"given":"Maogang","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Prithviraj","family":"Banerjee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Majid","family":"Sarrafzadeh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1998,11,20]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1999\/042648.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/vlsi\/1999\/042648.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1999\/42648","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T15:17:41Z","timestamp":1723216661000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1999\/42648"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,11,20]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1999,1]]}},"alternative-id":["10.1155\/1999\/42648"],"URL":"https:\/\/doi.org\/10.1155\/1999\/42648","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,11,20]]},"assertion":[{"value":"1998-09-07","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1998-11-20","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1998-11-20","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}