{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T11:05:05Z","timestamp":1740135905972,"version":"3.37.3"},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":407,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/100007140","name":"Synopsys","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100007140","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1999,1]]},"abstract":"<jats:p>A new hierarchical layout <jats:italic>vs.<\/jats:italic> schematic (LVS) comparison system for layout verification\nhas been developed. The schematic hierarchy is restructured to remove ambiguities for\nconsistent hierarchical matching. Then the circuit hierarchy is reconstructed from the\nlayout netlist by using a modified SubGemini algorithm recursively in bottom\u2010up fashion.\nFor efficiency, simple gates are found by using a fast rule\u2010based pattern matching\nalgorithm during preprocessing. Experimental results show that our hierarchical netlist\ncomparison technique is effective and efficient in CPU time and in memory usage,\nespecially when the circuit is large and hierarchically structured.<\/jats:p>","DOI":"10.1155\/1999\/50892","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:37Z","timestamp":1190120317000},"page":"117-125","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Hierarchy Restructuring for Hierarchical LVS Comparison"],"prefix":"10.1155","volume":"10","author":[{"given":"Wonjong","family":"Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hyunchul","family":"Shin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1998,11,20]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1999\/050892.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1999\/50892","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T15:17:40Z","timestamp":1723216660000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1999\/50892"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,11,20]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1999,1]]}},"alternative-id":["10.1155\/1999\/50892"],"URL":"https:\/\/doi.org\/10.1155\/1999\/50892","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,11,20]]},"assertion":[{"value":"1998-09-07","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1998-11-20","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1998-11-20","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}