{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T10:10:01Z","timestamp":1723198201504},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":652,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1999,1]]},"abstract":"<jats:p>It is well known that standard cells have been widely used to implement VLSI circuits in\nthe automation of physical design. Since one major aim of a cell\u2010based design is to minimize\ntotal layout area in a standard cell placement, the number of feedthrough cells will\nbe minimized to reduce total cell area in a standard cell placement. In this paper, first,\nwe model a partitioning\u2010based row assignment (PRA) problem to minimize the number\nof feedthrough cells in a standard cell placement. Furthermore, an integer linear programming\n(ILP) approach is proposed to solve the PRA problem in a standard cell\nplacement. Finally, the ILP approach has been implemented and two standard\u2010cell netlists,\nPrimary 1 and Primary 2, have been tested by the proposed approach, Bose\u2032s approach\n[4] and an exhaustive search approach, respectively. The experimental results show\nthat the ILP approach obtains fewer feedthrough cells than Bose\u2032s approach in a\npartitioning\u2010based standard cell placement.<\/jats:p>","DOI":"10.1155\/1999\/59138","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:37Z","timestamp":1190120317000},"page":"169-176","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["An ILP Formulation for Minimizing the Numberof Feedthrough Cells in a Standard Cell Placement"],"prefix":"10.1155","volume":"10","author":[{"given":"Jin-Tai","family":"Yan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1998,3,20]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1999\/059138.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1999\/59138","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T09:49:17Z","timestamp":1723196957000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1999\/59138"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,3,20]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1999,1]]}},"alternative-id":["10.1155\/1999\/59138"],"URL":"https:\/\/doi.org\/10.1155\/1999\/59138","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,3,20]]},"assertion":[{"value":"1996-11-17","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1998-03-20","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1998-03-20","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}