{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T10:10:01Z","timestamp":1723198201622},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":365,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1999,1]]},"abstract":"<jats:p>We develop an <jats:italic>O<\/jats:italic>(<jats:italic>p<\/jats:italic> log <jats:italic>n<\/jats:italic>) time algorithm to obtain optimal solutions to the <jats:italic>p<\/jats:italic>\u2010pin <jats:italic>n<\/jats:italic>\u2010net\nsingle channel performance\u2010driven implementation selection problem in which each\nmodule has at most two possible implementations (2\u2010PDMIS). Although Her, Wang\nand Wong [1] have also developed an <jats:italic>O<\/jats:italic>(<jats:italic>p<\/jats:italic> log <jats:italic>n<\/jats:italic>) algorithm for this problem, experiments\nindicate that our algorithm is twice as fast on small circuits and up to eleven times\nas fast on larger circuits. We also develop an <jats:italic>O<\/jats:italic>(<jats:italic>p<\/jats:italic><jats:italic>n<\/jats:italic><jats:sup><jats:italic>c<\/jats:italic>\u22121<\/jats:sup>) time algorithm for the c, c &gt; 1,\nchannel version of the 2\u2010PDMIS problem.<\/jats:p>","DOI":"10.1155\/1999\/67373","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:37Z","timestamp":1190120317000},"page":"237-247","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A Fast Algorithm for Performance\u2010Driven Module Implementation Selection"],"prefix":"10.1155","volume":"10","author":[{"given":"Edward Y. C.","family":"Cheng","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sartaj","family":"Sahni","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1999,2,8]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1999\/067373.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/vlsi\/1999\/067373.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1999\/67373","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T09:49:25Z","timestamp":1723196965000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1999\/67373"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,1]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1999,1]]}},"alternative-id":["10.1155\/1999\/67373"],"URL":"https:\/\/doi.org\/10.1155\/1999\/67373","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1999,1]]},"assertion":[{"value":"1998-03-24","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-02-08","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-02-08","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}