{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,21]],"date-time":"2025-04-21T05:02:35Z","timestamp":1745211755283},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":407,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1999,1]]},"abstract":"<jats:p>Important layout properties of electronic circuits include space requirements and\ninterconnection lengths. In the process of designing these circuits, a reliable pre\u2010layout\ninterconnection length estimation is essential for improving placement and routing\ntechniques. Donath found an upper bound for the average interconnection length that\nfollows the trends of experimentally observed average lengths. Yet, this upper bound\ndeviates from the experimental value by a factor <jats:italic>\u03b4<\/jats:italic>\u2009 \u2248 \u20092, which is not sufficiently accurate\nfor some applications. We show that we obtain a significantly more accurate estimate by\ntaking into account the inherent features of the optimal placement process.<\/jats:p>","DOI":"10.1155\/1999\/81698","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:37Z","timestamp":1190120317000},"page":"1-20","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":30,"title":["Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle"],"prefix":"10.1155","volume":"10","author":[{"given":"Dirk","family":"Stroobandt","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jan Van","family":"Campenhout","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1998,11,20]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1999\/081698.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1999\/81698","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T15:17:37Z","timestamp":1723216657000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1999\/81698"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,11,20]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1999,1]]}},"alternative-id":["10.1155\/1999\/81698"],"URL":"https:\/\/doi.org\/10.1155\/1999\/81698","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,11,20]]},"assertion":[{"value":"1998-09-07","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1998-11-20","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1998-11-20","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}