{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T10:10:01Z","timestamp":1723198201686},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":421,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1999,1]]},"abstract":"<jats:p>Many test schemes use signature analyzers to compact the responses of a circuit under\ntest. Unfortunately, there can be some faulty circuits with erroneous test responses but\nexactly the same signature as in the fault\u2010free case. Hence, methods are required to determine\nhow many faults become undetectable due to aliasing. Whereas previous work\nconcentrated on combinational circuits, this paper investigates signature analysis for\na wide range of sequential circuits, where the errors in successive responses are correlated.\nIt is shown that for almost all faults of these circuits the probability of aliasing\nin a signature analyzer with <jats:italic>k<\/jats:italic> bits asymptotically approaches 2<jats:sup>\u2212<jats:italic>k<\/jats:italic><\/jats:sup> or is 0 if a signature\nanalyzer with an irreducible characteristic polynomial is used and certain test lengths\nare avoided. The limiting value can be used as a good approximation for practical test\nlengths. These results are particularly useful for advanced built\u2010in self\u2010test techniques\nwith low hardware overhead.<\/jats:p>","DOI":"10.1155\/1999\/97179","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:37Z","timestamp":1190120317000},"page":"127-141","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Signature Analysis for Test Responses of Sequential Circuits"],"prefix":"10.1155","volume":"10","author":[{"given":"Albrecht P.","family":"Stroele","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1998,11,6]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1999\/097179.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1999\/97179","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T09:49:23Z","timestamp":1723196963000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1999\/97179"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,11,6]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1999,1]]}},"alternative-id":["10.1155\/1999\/97179"],"URL":"https:\/\/doi.org\/10.1155\/1999\/97179","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1998,11,6]]},"assertion":[{"value":"1997-11-10","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1998-11-06","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1998-11-06","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}