{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:40:01Z","timestamp":1723203601450},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":139,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2000,1]]},"abstract":"<jats:p>Delay time estimation in simulation or design verification step during a design cycle\nhas become more and more important as the meaning of performance prediction. This\npaper proposed a delay estimation model for digital CMOS circuits, which works\nin gate\u2010level but the modeling process includes the characteristics of MOSFETs. This\nmodel can handle the variation according to the kind of gates, input transition time,\noutput load(fan\u2010out), and transistor sizes of a gate. The procedure to find the general\nmodel was that, a delay model for CMOS inverter was extracted first, then it was\nextended to other gate by converting it into an equivalent inverter. The resulting model\nwas evaluated and compared with SPICE simulation, which showed that the proposed\nmodel has the accuracy of less than 5% relative error rate to the SPICE results for each\ncase and the speed of about 70 times faster than SPICE.<\/jats:p>","DOI":"10.1155\/2000\/18189","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:57Z","timestamp":1190120337000},"page":"161-173","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Delay Time Estimation Model for Large Digital CMOS Circuits"],"prefix":"10.1155","volume":"11","author":[{"given":"Dong-Wook","family":"Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tae-Yong","family":"Choi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1999,8,15]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2000\/018189.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2000\/18189","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:24:09Z","timestamp":1723202649000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2000\/18189"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,8,15]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2000,1]]}},"alternative-id":["10.1155\/2000\/18189"],"URL":"https:\/\/doi.org\/10.1155\/2000\/18189","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1999,8,15]]},"assertion":[{"value":"1999-02-02","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-08-15","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-08-15","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}